1. Field of the Invention
The technology disclosed herein relates to an on-ship signal waveform measurement apparatus for, on multi-channels, measuring signal waveforms at detection points on fixed voltage wiring lines such as internal signals, power source voltages, ground voltages, well voltages, and substrate voltages of a semiconductor large-scale integrated circuit (LSI), and a signal waveform measuring system including the on-ship signal waveform measurement apparatus. The technology disclosed herein further relates to a sampling timing signal generator for use in the signal waveform measurement system.
2. Description of the Related Art
With an increased degree of micro-fabrication in the semiconductor wafer fabrication process, the scale of the circuits mounted on LSI chips becomes larger. In recent years, a mixed signal system LSI has been commonly employed in which different types of signal processing functions (such as an analog processing and a digital processing or a high frequency radio communication processing and a baseband data processing) are integrated on a single chip. However, since such an LSI is configured so that many functional circuits are integrated on the LSI chip, the operation states of respective functional circuits cannot be observed from outside of the chip. As a result, it is difficult to perform a fault analysis in a case of an operation fault. On the other hand, considerations of noise generated in a power source, a ground, a well, and a substrate have been increasingly important in a high-rate and low power consumption LSI. Thus, the need for on-chip measurement and evaluation of such noise on the LSI chip has been growing. The technical background is disclosed in the following patent documents 1-3 and non-patent documents 1-2.
(a) Patent Document 1: Japanese patent laid-open publication No. JP-10-123215-A;
(b) Patent Document 2: Japanese patent laid-open publication No. JP-2001-077160-A;
(c) Patent Document 3: Japanese Patent laid-open publication No. JP-2003-028898-A;
(d) Non-Patent Document 1: Makoto Nagata et al., “Effects of Power-Supply Parasitic Components on Substrate Noise Generation in Large-Scale Digital Circuits”, 2001 Symposium on VLSI Circuits Digest of Technical Papers, #15-1, Kyoto in Japan, pp. 159-162, June 2001; and
(e) Non-Patent Document 2: Koichiro Noguchi et al., “On-Chip Power Source/Ground Measurement Technique”, Proceedings of the Seventh System LSI Workshop, Non-regular Technical Committee of The IEICE (Institute of Electronics, Information and Communication Engineers) on ICD (Integrated Circuits and Devices), pp. 287-290, November 2003.
In order to meet the above need, it is effective to mount a function that measures an internal signal on the LSI chip. Conventionally, there has been known a technique capable of measuring a noise distribution on the LSI chip by arraying a probing front-end (FE) circuit constituted by a source follower (SF) circuit and a latch comparator (LC) (See the Non-Patent Document 1). However, this technique has the following problems. If only the probing front-end circuit is mounted on an LSI chip, the number of pins required for measurement becomes larger, and the performance required by an external measurement unit becomes higher. This then this leads to an increase in the manufacturing cost. In order to solve these problems, there was proposed an on-chip configuration in which not only the probing front-end circuit but also a timing signal generation circuit and a reference voltage generation mechanism are integrated on an IC chip (See the Non-Patent Document 2).
However, this technique still has the following problems. It is still necessary to reduce the measurement time, to reduce the chip area, and to ensure a higher measurement precision in multi-channel configuration. Therefore, this measurement system functions insufficiently as means for, on multi-channels, measuring various kinds of waveforms such as the internal signal and noises of the power source voltage, the ground voltage, the well voltage, and the substrate voltage of the LSI.